Verifying external interrupts of embedded microprocessor in SoC with on-chip bus

The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with other IP components, they suffer from the complicated bus protocol and IP conflict problems. This paper proposes a automatic method to verify the microprocessor external interrupt behaviors on the OCB. The verification approach is based on the Processor External Interrupt Verification Tool (PEVT) whose simulation environment is direct-connected memory. In this paper, we implement the PEVT-SoC and successfully verify two SoC platforms, one academic microprocessor and one public domain microprocessor. An interesting bug appears that is impossible to be discovered in the memory bus and not easy to be identified on the OCB. The result shows that the PEVT-SoC effectively shortens the verification time regardless of the system complexity and can be easily migrated to different platforms/microprocessors. With little human effort, even an inexperience designer can generate extensive verification cases in a systematic way.