DocumentCode
3487414
Title
Placement based multiplier rewiring for cell-based designs
Author
Mo, Fan ; Brayton, Robert K.
Author_Institution
Synplicity, Sunnyvale, CA
fYear
2008
fDate
10-13 Nov. 2008
Firstpage
430
Lastpage
433
Abstract
We present an algorithm for improving the performance of carry-save-adder (CSA) style multipliers. Based on placement information, the algorithm exploits the arithmetic equivalence in the CSA multipliers and rewires to improve the slack of the multiplier.
Keywords
digital signal processing chips; integrated circuit design; logic CAD; microprocessor chips; multiplying circuits; carry-save-adder multipliers; cell-based designs; digital integrated circuit designs; digital signal processors; microprocessors; placement based multiplier rewiring; Adders; Algorithm design and analysis; Arithmetic; Circuits; Delay estimation; Network topology; Pins; Signal processing algorithms; Timing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-2819-9
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2008.4681611
Filename
4681611
Link To Document