Simulation of the effects of manufacturing process variations on the characteristics of SOI MOSFETs

Author

Sanders, T.J. ; Phelps, M.J.

Author_Institution

AET Inc., USA

fYear

1995

fDate

3-5 Oct 1995

Firstpage

24

Lastpage

25

Abstract

Successful scaling of SOI MOSFETs to deep sub-micron features for use in high density and low power applications will require a thorough understanding of the effect of process variation on device yield. Manufacturing steps that contribute most to device parameter variation must be identified so that tolerances can be tightened. This paper shows that Design of Experiments (DoE) methodology can be applied to commercial process and device simulation packages to gain insight into the process flow of SOI devices and to identify possible challenges to be met in the fabrication of future devices

Keywords

MOSFET; design of experiments; semiconductor process modelling; silicon-on-insulator; SOI MOSFETs; deep sub-micron devices; design of experiments; device simulation; fabrication; high density low power applications; manufacturing process variations; process simulation; scaling; tolerances; yield; Design automation; Design optimization; Fabrication; Input variables; MOSFETs; Manufacturing processes; Packaging; Statistics; Threshold voltage; US Department of Energy;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1995. Proceedings., 1995 IEEE International

Conference_Location

Tucson, AZ

Print_ISBN

0-7803-2547-8

Type

conf

DOI

10.1109/SOI.1995.526442

Filename

526442