DDR2/DDR3-based ultra-rapid reconfiguration controller

Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency using low-latency memory to store bitstream. State-of-the-art solutions use on-chip memory (BRAM) to store bitstreams and operate at very high frequency. However, their major drawback is the limit of bit-stream storage because of the limited number of available on-chip memory element. In this paper, we present an ultra-fast reconfiguration controller based on DDR2/DDR3 SDRAM to reach the throughput limit of Virtex-5 and Virtex-6 reconfiguration port (1.48 GB/s). This controller fulfills the drawback of state-of-the-art rapid controllers which use on-chip BRAM to store bitstreams. Our proposed controller can not only reach the fastest reconfiguration speed (ICAP limit) but also offer high capacity of bitstream storage.