A 0.042-mm2 fully integrated analog PLL with stacked capacitor-inductor in 45nm CMOS

We present a fully integrated Phase Locked Loop in an advanced 45 nm CMOS technology. The loop filter is integrated on chip under the voltage-controlled oscillator inductor, resulting in significant area savings. The whole PLL measures only 280 mum by 150 mum. The PLL has a dual-band output for 2-2.5 GHz and 4-5 GHz. The circuit operates from a 0.85 V supply and consumes 15.3 mW for a -120 dBc/Hz phase noise at a 1 MHz offset from a 2.0 to 2.5 GHz carrier.