• DocumentCode
    3490879
  • Title

    A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor

  • Author

    Xiao Yan Yu ; Chan, Yiu-Hing ; Curran, Brian ; Schwarz, Eric ; Kelly, Michael ; Fleischer, Bruce

  • Author_Institution
    IBM Syst. & Technol. Group, Poughkeepsie, NY
  • fYear
    2006
  • fDate
    19-21 Sept. 2006
  • Firstpage
    166
  • Lastpage
    169
  • Abstract
    A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process technology. Efficient use of static circuits and careful balance of the look-ahead tree enable our floating point design to operate beyond 5GHz with 1.1 V supply
  • Keywords
    adders; floating point arithmetic; microprocessor chips; silicon-on-insulator; 1.1 V; 128 bit; 65 nm; POWER6 floating-point unit; POWER6 processor; SOI process; binary floating-point adder; carry adder; look-ahead tree; static circuits; Adders; Circuits; Delay; Frequency; Logic; Microprocessors; Modems; Pipelines; Space technology; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
  • Conference_Location
    Montreux
  • ISSN
    1930-8833
  • Print_ISBN
    1-4244-0303-0
  • Type

    conf

  • DOI
    10.1109/ESSCIR.2006.307557
  • Filename
    4099730
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3490879