Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs

Author

Naseer, Riaz ; Draper, Jeff

Author_Institution

Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

222

Lastpage

225

Abstract

The range of SRAM multi-bit upsets (MBU) in sub-100 nm technologies is characterized using irradiation tests on two prototype ICs, developed in 90 nm commercial processes. Results reveal that MBU, as large as 13-bit, can occur in these technologies, limiting the efficacy of conventional SEC-DED error-correcting codes (ECC). A double-error correcting (DEC) ECC implementation technique suitable for SRAM applications is presented. Results show that this DEC scheme reduces errors by 98.5% compared to only 44% reduction by conventional SEC-DED ECC.

Keywords

SRAM chips; error correction codes; integrated circuit testing; radiation hardening (electronics); ECC implementation technique; SEC-DED error-correcting codes; SRAM multibit upset; double-error correcting; irradiation tests; parallel double error correcting code; size 90 nm; Application specific integrated circuits; Error correction; Error correction codes; Iterative decoding; Marine technology; Protection; Prototypes; Random access memory; Space technology; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Conference_Location

Edinburgh

ISSN

1930-8833

Print_ISBN

978-1-4244-2361-3

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2008.4681832

Filename

4681832