Light Speed Labeling for RISC architectures

Author

Lacassagne, L. ; Zavidovique, B.

Author_Institution

Inst. d´´Electron. Fondamentale (IEF/AXIS), Univ. Paris Sud, Paris, France

fYear

2009

fDate

7-10 Nov. 2009

Firstpage

3245

Lastpage

3248

Abstract

This article introduces a fast algorithm for Connected Component Labeling of binary images called Light Speed Labeling. It is segment-based and a line-relative labeling that was especially thought for RISC computers. An extensive benchmark on both structured and unstructured images substanciates that the algorithm, the way it is designed, is faster and more runtime predictable than Wu´s algorithm claimed to be the world fastest in 2007.

Keywords

image segmentation; reduced instruction set computing; RISC architectures; RISC computers; Wu algorithm; binary images; connected component labeling; light speed labeling; line relative labeling; Algorithm design and analysis; Computer architecture; Filtering algorithms; Geophysics computing; Image processing; Image segmentation; Labeling; Pipelines; Reduced instruction set computing; Testing; Connected Component Labeling; Real-Time implementation; run length coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing (ICIP), 2009 16th IEEE International Conference on

Conference_Location

Cairo

ISSN

1522-4880

Print_ISBN

978-1-4244-5653-6

Electronic_ISBN

1522-4880

Type

conf

DOI

10.1109/ICIP.2009.5414352

Filename

5414352

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3492813