Performance improvement of fast packet switching by LDOLL queueing

Low delay or low loss (LDOLL) queuing policies for asynchronous transfer model (ATM) fast packet switching allow either retrieval priority or storage priority to be given to the ATM cells of traffic streams with different performance requirements. The improvements in performance that can be achieved by using one bit in the ATM cell header to make the binary LDOLL distinction are analyzed. In the analysis, simulation of the level, where the cell transmission rate of a source may vary between zero and the peak rate and computation at the level, where queuing of individual cells is considered, are combined. It is shown that LDOLL queuing, compared with FIFO queuing in ATM switches, can reduce cell loss probability by many orders of magnitude for low loss traffic. Low delay traffic incurs a slightly higher cell loss which is compensated with a reduced cell delay mean and variance