Efficient implementation of multiplier-free decimation filters for ΣΔ A/D conversion

This paper describes a design technique for multiplier-free FIR filters to be used as decimation stages in ΣΔ converters. The proposed solution used right shifters and accumulators to implement power-of-two multiplications; moreover, it minimizes the number of right shifts in the whole filter, thus allowing high clock rate operation. The resulting architecture reduces the area requirement with respect to conventional multiplier-based solutions