Electrical design of the SPARCcenter 2000 multi/processors server using low voltage swing CMOS

One of the major challenges to design a high performance computer system is to predict accurate interchip timing as well as control the electrical noises such as crosstalk, reflections and Ldi/dt noise. As board level clock frequency exceeds 50 MHz, using conventional full swing CMOS driver driving heavily loaded long bus on PCB or a backplane and obtaining a desirable result becomes increasingly difficult. In order to achieve higher performance on board with a heavily loaded long bus, low voltage 800 mV swing CMOS transmission line transceiver (Gunning et al., 1992), referred here as GTL, was developed. In this paper, the system electrical design methodology for designing a low cost and high performance 20 super SPARC processor server (SPARCcenter 2000) using this 800 mV swing transceiver designed in 1.0 micron CMOS gate array is discussed along with some laboratory measurement results.