A two-level pipelined systolic array chip for computing the discrete cosine transform

Author

Jiun-In Guo ; Chi-Min Liu ; Jen, Chein-Weit

Author_Institution

Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1993

fDate

1993

Firstpage

199

Lastpage

203

Abstract

A two-level pipelined systolic array chip for the discrete cosine transform (DCT) is presented. This chip is based on a new memory-based systolic algorithm which not only uses small ROMs and adders to realize the multiplications but also owns good data locality. Therefore, this chip possesses outstanding performance in hardware cost, computing speeds, the number of I/O channels, and the I/O bandwidth.

Keywords

digital arithmetic; discrete cosine transforms; integrated circuit technology; logic CAD; logic arrays; multiplying circuits; pipeline processing; systolic arrays; DCT; GENESIL CAD tool; I/O bandwidth; I/O channels; ROM; VLSI; adders; computing speeds; data locality; discrete cosine transform; hardware cost; memory-based systolic algorithm; multiplications; two-level pipelined systolic array chip; Bandwidth; Computer architecture; Costs; Discrete cosine transforms; Distributed computing; Hardware; Read only memory; Shift registers; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on

Conference_Location

Taipei, Taiwan

ISSN

1524-766X

Print_ISBN

0-7803-0978-2

Type

conf

DOI

10.1109/VTSA.1993.263606

Filename

263606