• DocumentCode
    3499836
  • Title

    CMA-2 : The second prototype of a low power reconfigurable accelerator

  • Author

    Izawa, Mai ; Ozaki, Nobuaki ; Yasuda, Yoshihiro ; Kimura, Masayuki

  • Author_Institution
    Hideharu Amano Keio Univ., Japan
  • fYear
    2012
  • fDate
    Jan. 30 2012-Feb. 2 2012
  • Firstpage
    471
  • Lastpage
    472
  • Abstract
    A design, implementation and evaluation of low power accelerator CMA-2 were introduced. Evaluation result with real chip shows that the maximum energy efficiency is 233.7 MOPS/mW.
  • Keywords
    low-power electronics; memory architecture; microprocessor chips; reconfigurable architectures; cool mega-array; low power accelerator CMA-2; low power reconfigurable accelerator; maximum energy efficiency; real chip; Arrays; Clocks; Delay; Layout; Pipelines; Prototypes; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
  • Conference_Location
    Sydney, NSW
  • ISSN
    2153-6961
  • Print_ISBN
    978-1-4673-0770-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2012.6164996
  • Filename
    6164996
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3499836