Implementation of RNS analysis and synthesis filter banks for the orthogonal discrete wavelet transform over FPL devices

Author

Ramírez, J. ; García, A. ; Parrilla, L. ; Lloris, A. ; Fernández, P.G.

Author_Institution

Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain

Volume

3

fYear

2000

fDate

2000

Firstpage

1170

Abstract

RNS architectures to compute the orthogonal DWT and its inverse are shown. The relation between the coefficients of the analysis and synthesis filters allows one to halve the number of required LUTs and modular adders. Simulations of one- and two- octave implementations using VHDL and FPL devices show a performance advantage of up to 23.45 and 96.58% when compared to the 2´s complement arithmetic versions, respectively

Keywords

adders; digital signal processing chips; discrete wavelet transforms; hardware description languages; parallel architectures; pipeline processing; programmable logic devices; residue number systems; table lookup; FPL devices; LUTs; RNS analysis filter banks; RNS synthesis filter banks; VHDL; field-programmable logic; modular adders; one-octave implementations; orthogonal discrete wavelet transform; two-octave implementations; Arithmetic; Channel bank filters; Digital signal processing; Discrete wavelet transforms; Dynamic range; Filter bank; Logic devices; Table lookup; Throughput; Wavelet analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951423

Filename

951423