Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion

This paper presents a novel approach to improve the existing Binary-to-RNS multi-moduli architectures. These architectures reduce the complexity by sharing common intermediate results among various RNS moduli channels. Two types of multi-moduli architectures are distinguished depending on whether the functionality is implemented serially or in parallel. A novel choice of the weights associated to the inputs provides huge improvement when applied to the most efficient topology known to date. Experimental results suggest that the proposed memoryless multi-moduli architectures achieve speedups of 2.02 and 1.79 for parallel and serial implementations, respectively, in comparison with the most efficient state-of-the-art structures. Furthermore, such implementations herein proposed have demonstrated that area reductions of 5.02% and 44.02% are achieved for parallel and serial structures, respectively.