A totally self-checking S-box architecture for the advanced encryption standard

The advanced encryption standard (AES) has been widely used in many applications since adopted by the NIST in 2001. AES is often implemented in hardware for security purposes, but because of the complex nature of the algorithm, reliability is a major concern. The use of error-detecting codes (EDCs) and physical duplication are generally the two methods that have been used for fault detection, although EDCs are costly in run-time and duplication is costly in real-estate. This paper proposes a method for making the S-box, which is by far the critical component of AES, totally self-checking using pseudo-nMOS technology. The fault detection method proposed in this paper has a lower latency than EDCs and requires less overhead than duplication. Although this method is shown only in constructing the S-box, the method can be scaled up to make the entire AES algorithm totally self-checking