DocumentCode
3503245
Title
A generalized block distribution algorithm for fast carry-skip adder design
Author
Yu, C.C. ; Lin, C.S. ; Liu, B.-D.
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
2
fYear
1999
fDate
36495
Firstpage
844
Abstract
In this paper, we describe a generalized block distribution algorithm to determine the block sizes. Furthermore, we employ an alternative carry-skip circuit in each block to accelerate the carry propagation speed and lower the power consumption. Various supply voltages were used during the simulation phase. The simulation results reveal that the proposed scheme can provide faster speed and lower power consumption than those of the existing carry-skip adder. These power and speed advantages are maintained down to a 1.2 V power supply. It is suitable for low-power high-speed adder implementation
Keywords
adders; logic design; low-power electronics; 1.2 V; carry-skip adder; circuit design; circuit simulation; generalized block distribution algorithm; low-power high-speed circuit; Acceleration; Adders; Algorithm design and analysis; Arithmetic; Circuit simulation; Computational modeling; Energy consumption; Propagation delay; Signal generators; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 99. Proceedings of the IEEE Region 10 Conference
Conference_Location
Cheju Island
Print_ISBN
0-7803-5739-6
Type
conf
DOI
10.1109/TENCON.1999.818550
Filename
818550
Link To Document