Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators

One of the major challenges in automated synthesis of reconfigurable accelerators is to create efficient designs that conform to the resource capacity of the target device. This work concerns estimation of the hardware cost before actually attempting the synthesis of streaming accelerators on reconfigurable platforms. Specifically, our proposed framework tackles the problem of presynthesis estimation of data queuing cost, while incorporating the potential impact of resource constraints on the final implementation. We present a probabilistic push-and-pull approach for register queue size estimation of a streaming data flow graph. We evaluated our techniques using an industrial tool/low. For the register queue sizes our estimations are within the range of -14.4% to 12.4% on an average, for various resource constraints on a set of multimedia applications