Developing a transient induced latch-up standard for testing integrated circuits

Author

Kelly, M. ; Henry, L.G. ; Barth, J. ; Weiss, G. ; Chaine, M. ; Gieser, H. ; Bonfert, D. ; Meuse, T. ; Gross, V. ; Hatchard, C. ; Morgan, I.

Author_Institution

Delphi Delco Electron. Syst., Kokomo, IN, USA

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

178

Lastpage

189

Abstract

This paper presents the results of a search for a more effective stimulus suitable for assessing the latch-up susceptibility of integrated circuits. Different transient stimuli and amplitudes were found to have varying effectiveness in creating a latch event. The investigation also identified the inadequate response and recovery of existing test system power supplies and need for appropriate isolation techniques.

Keywords

electrostatic discharge; integrated circuit reliability; integrated circuit testing; power supply circuits; standards; test equipment; transient analysis; IC testing; integrated circuits; latch event creation; latch-up stimulus; latch-up susceptibility; power supply isolation techniques; test system power supply recovery; test system power supply response; transient amplitudes; transient induced latch-up standard; transient stimuli; Bipolar transistors; Circuit testing; Electrostatic discharge; Instruments; Integrated circuit testing; Microelectronics; Power supplies; Pulsed power supplies; Standards development; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.819004

Filename

819004