Predictive Load Balancing for Interconnected FPGAs

A field programmable gate array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism over the alternative approach of software running on a general-purpose microprocessor. However, the increasing disparity between the logic speed and density of a state-of-the-art FPGA versus a state-of-the-art microprocessor has already begun to negate the benefits of this increased functional parallelism for all but a limited set of applications. The authors believe that the solution to this problem is to construct distributed multi-FPGA architectures to aggregate the parallelism of multiple FPGAs. Such a system would require a high-capacity interconnect, and thus arranging the FPGAs onto a scalable direct network was proposed. This strategy requires each FPGA to contain an integrated router that must share the logic fabric with the application logic. This paper proposed a novel routing technique that can significantly boost such a network´s capacity and be implemented into compact and efficient routers. The authors begin with an existing lightweight routing algorithm and augment it with a novel technique called predictive load balancing, where routers collect information about the blocking behavior on their output ports and use this information when making routing decisions