• DocumentCode
    3512300
  • Title

    Modified hybrid symmetrical multilevel inverter

  • Author

    Korbes, Daniel ; Mussa, Samir Ahmad ; Ruiz-Caballero, Domingo

  • Author_Institution
    Power Electron. Inst. (INEP), Fed. Univ. of Santa Catarina (UFSC), Florianópolis, Brazil
  • fYear
    2012
  • fDate
    5-9 Feb. 2012
  • Firstpage
    1615
  • Lastpage
    1618
  • Abstract
    Even more the needs of efficiency and productivity are required in industrial processes. Medium and high voltage inverter topologies are used in high scale industrial processes to achieve these goals. This work presents two variants of a modified hybrid symmetrical multilevel inverter topology based in [8] using Half Bridge commutation cells, proper to use in medium voltage levels. These topologies are able to create a 7-level phase-voltage waveform and a 13-level line-voltage waveform. A reduction in the number of switches and isolated sources is achieved when compared to traditional multilevel topologies, specially the cascaded topologies. A low power prototype was assembled using a programmable device (FPGA) and a modular platform developed to test new topologies.
  • Keywords
    field programmable gate arrays; invertors; 13-level line-voltage waveform; 7-level phase-voltage waveform; FPGA; half-bridge commutation cells; high-scale industrial process; high-voltage inverter topology; isolated source reduction; medium-voltage inverter topology; modified hybrid symmetrical multilevel inverter topology; modular platform; programmable device; switch reduction; Frequency modulation; Inverters; Pulse width modulation; Switches; Topology; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    978-1-4577-1215-9
  • Electronic_ISBN
    978-1-4577-1214-2
  • Type

    conf

  • DOI
    10.1109/APEC.2012.6166036
  • Filename
    6166036