Improving resource utilization in an multiple asynchronous ALU DSP architecture

A current trend in digital signal processing is to reduce power and energy consumption. The use of asynchronous designs is one of the possible ways to achieve these goals, but the nature of these circuits requires different modeling schemes. We present in this paper our own model for a novel DSP architecture comprising multiple asynchronous cores and ALUs per core. Our approach shows how to match the inherent parallelism of the architecture to its target application. Our technique also proves useful to guide the mapping decisions of a target algorithm onto an MPSoC architecture, in order to increase the throughput by multithreading several packets.