Optimization of the drive circuit for enhancement mode power GaN FETs in DC-DC converters

This paper discusses the practical concerns and optimization of the drive circuit for enhancement mode Gallium-Nitride (GaN) power transistors in dc-dc converters. The GaN FET´s 6.0V absolute maximum gate voltage rating and ultra low threshold voltage impose strict constrains on the drive circuit. It is critical to achieve precise gate voltage limit, realize a low impedance gate signal path, and meet the stringent noise immunity requirements by optimizing the gate drive circuit. Prototype converters were built and experimental results are presented as proof of concept.