A single-chip MPEG-2 video encoder/decoder for consumer applications

Author

Chen, C.T. ; Chen, T.C. ; Feng, C. ; Huang, C.-C. ; Jeng, F.-C. ; Konstantinides, K. ; Lin, E.H. ; Smolenski, M. ; Haly, E.

Author_Institution

Stream Machine, San Jose, CA, USA

Volume

4

fYear

1999

fDate

1999

Firstpage

252

Abstract

In this paper we present a single chip MPEG-2, MP@ML, video encoder/decoder. It combines a RISC core and several dedicated processing units organized as a process pipeline. It includes a generic 16-bit host interface and direct interfaces to video modulators and demodulators. It has been implemented using a standard-cell library, in a four-layer metal, 0.35 μm CMOS technology. Its small size (less than 3 million transistors) and low implementation cost make it suitable for a wide range of consumer applications

Keywords

CMOS integrated circuits; decoding; demodulators; encoding; modulators; reduced instruction set computing; video codecs; 16-bit host interface; CMOS technology; MP@ML; MPEG-2; RISC core; consumer applications; dedicated processing units; demodulators; direct interfaces; low implementation cost; process pipeline; single-chip MPEG-2 video encoder/decoder; standard-cell library; video modulators; CMOS technology; Codecs; Costs; Decoding; Encoding; Reduced instruction set computing; Satellite broadcasting; Size control; Streaming media; TV;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1999. ICIP 99. Proceedings. 1999 International Conference on

Conference_Location

Kobe

Print_ISBN

0-7803-5467-2

Type

conf

DOI

10.1109/ICIP.1999.819589

Filename

819589