Parametric design study for minimized warpage of WL-CSP

WL-CSP (wafer level - chip scale package) has many advantages such as low cost, easy fabrication and ultimate miniature size, even though solder joint reliability (SJR) of conventional WL-CSP is critical weak point of the technology. Therefore, many advanced structure of WL-CSP has been developed to improve SJR such as using Cu post covered with encapsulation material. One of advanced WL-CSP is using encapsulated e double solder bump structure that the first bump is covered with epoxy molding compound (EMC) to protect. Fig.1 shows both conventional and encapsulated double bump type WL-CSP structure. However, the warpage of this advanced WL-CSP is much higher than conventional one due to CTE mismatch between silicon wafer and EMC material, which generates failure such as wafer crack or manufacturing difficulty such as process handling. In this paper, WL-CSP which has 120 mum EMC thickness on 6 inch wafer has been developed for advanced high I/O density applications. The warpage of WL-CSP after EMC curing process is considered. 3D thermo-mechanical FEM simulation is carried out the warpage distribution after curing process. The results also present the main factor in materials to affect the WL-CSP warpage. The lower Youngpsilas modulus and EMC CTE for encapsulation achieves less warpage. Furthermore, we studied some structures to reduce the warpage of WLCSP such as adding other material on backside of wafer and using patterned EMC. Both structures can make the WL-CSP structure balanced.