FPGA design security with time division multiplexed PUFs

With the advent of FPGAs, high performance application specific processors can be designed and produced with little investment using a software-like methodology. This ease of design, on the other hand, creates a lot of opportunity for design theft through cloning. A solution to this is bitstream encryption, which is a feature available in rather pricey FPGAs. Physically Unclonable Functions (PUFs) make the same capability possible in ordinary FPGAs. A PUF module provides a signature unique to each chip with the help of manufacturing variations. However, a stable signature requires quite a few bits of PUF, which may not fit in small FPGAs. This paper presents a new PUF based design methodology, which we call Time Division Multiplexed PUF (TDM-PUF). A TDM-PUF divides a single and long PUF into several smaller PUFs run in different time segments. This is made possible by the widely available dynamic partial configuration capability of FPGAs.