SiC Power Electronics Packaging Prognostics

Electronic packages may be subjected to a wide array of potential failure modes throughout their useful lifetimes. Package design for SiC power electronic devices must account for a number of these potential failure modes, especially those due to the high operating temperatures and power levels at which the semiconductor must operate. High temperature SiC package design is still a relatively immature technology with little information published which discusses package failure. Conversely, the current generation of Si-based packaging technology is quite mature and, therefore, may be capable of providing useful insight with regards to the dominant failures that may be seen in the operational life of SiC and Si high power packaging. A literature survey completed produced considerable information relating to the many known failure mechanisms for Si-based electronic packages. Using the information obtained from this survey, a Failure Mode and Effects Analysis (FMEA) was completed and failure modes considered to have high probability of occurrence in a SiC- based package were identified. The dominant failure modes targeted were bond wire fatigue, solder joint fatigue and encapsulant breakdown. Life models for the fatigue failures were developed using forms of the Coffin-Manson relationship. A life model for encapsulant breakdown was also developed using dielectric fatigue and Partial Discharge (PD) mechanisms through the Dissado-Mazzanti-Montanari (DMM) model and PD model, respectively. These above models will then be used to prognosticate the electronic packaging.