A multilayer process for fine-pitch assemblies on molded interconnect devices (MIDs)

The miniaturization of overall systems plays a key role for the propagation of technological applications. To meet future requirements in size decreasing environments especially the packaging and mounting of silicon devices needs new impulses. 3D-MIDs (3-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. The integration of various functionalities (electrical connections, housing, thermal management, mechanical support) in one 3-dimensional shaped circuit carrier makes a further system shrinking possible. The compatibility between 3D-MIDs and high density fine-pitch semiconductor packages (like BGAs, MCMs, CSPs or even bare dies) is limited. Due to lack of a 3-dimensional multilayer technology the wiring of semiconductors with a high I/O count is critical. Therefore a new 3D-MID multilayer process is developed and combined with an established 3D-MID metallization process. The new multilayer process is investigated with respect to its electrical and mechanical behavior. A demonstrator was fabricated to perform desired tests.