Shock test evaluation for electronic packages

The need for continuously integrated and miniaturized microelectronics packages for mobiles applications has promoted and will amplify the development and the industrialization of wafer level chip scale packages (WLCSP). Some assembly challenges have already been overcome and some others will need to be validated with the trend to smaller interconnections associated with reduced pitches. In parallel with these challenges, the printed wiring board (PWB) assembly performances of such WLCSP is essential to their extension. In some cases, it is considered as a limiting factor because the shocks that the package can withstand during the assembly process are more critical on bare silicon compared to plastic packages.