Logic-Based Mega-Bit CuxSiyO emRRAM with Excellent Scalability Down to 22nm Node for post-emFLASH SOC Era

Excellent scalability of a novel Cu_xSi_yO emRRAM down to 22 nm node is demonstrated based on statistical data of 1 Mb test chip for the first time. The integration utilizes the standard logic process and the RRAM size is shrunk by spacer pattern technology. The reset current decreases by 5X from 130nm to 22nm node with maintaining robust data retention (10yrs. @150°C), good resistance distribution (with 10X window @125°C), significant read disturbance immunity (after 1010 cycles @0.5V, 50ns pulse), acceptable fast speed (set 100ns; reset 60us), and competitive cost effectiveness (no dedicated tools). This solution is promising in the advanced logic node for SOC applications of post-emFLASH era.