DocumentCode
3519102
Title
Encapsulation challenges for wafer level packaging
Author
Th, E.K. ; Hao, J.Y. ; Ding, J.P. ; Li, Q.F. ; Chan, W.L. ; Ho, S.C. ; Huang, H.M. ; Jiang, Y.J.
Author_Institution
ASM Technol. Singapore Pte Ltd., Singapore, Singapore
fYear
2009
fDate
9-11 Dec. 2009
Firstpage
903
Lastpage
908
Abstract
The interest of user for WLP has been raised because of benefits such as reduced package thickness, fan-out capability, high I/O, substrate-less process, integration of passives into structure, good thermal and electrical performance. The objective of this paper is to delineate technical challenges and issues that potential adopter of wafer level molding will face, technological solution availability and the broad application of WLP using granulated epoxy and liquid encapsulant such as epoxy, hybrid of epoxy-silicone, silicone. Result base on actual molding trial indicates among the different form of wafer level molding the challenges being faced are similar, including co-planarity, warpage, die shifting, coefficient of thermal expansion matching, incomplete filling, MBF and voiding.
Keywords
encapsulation; plastic packaging; thermal expansion; wafer level packaging; die shift; encapsulation; granulated epoxy; liquid encapsulant; mold bleed flashing; package thickness; plastic encapsulated electronics; thermal expansion; wafer level packaging; Assembly; Costs; Electronic packaging thermal management; Electronics packaging; Encapsulation; Filling; Manufacturing; Packaging machines; Plastic packaging; Wafer scale integration; Co-planarity; Die Shift (DS); Mold Bleed Flashing (MBF); PEMs (plastic encapsulated microelectronics); Tape crinkle Incomplete Filling; Voiding; WLP (Wafer Level Package); Wafer Level Molding (WLM); Warpage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
Conference_Location
Singapore
Print_ISBN
978-1-4244-5099-2
Electronic_ISBN
978-1-4244-5100-5
Type
conf
DOI
10.1109/EPTC.2009.5416414
Filename
5416414
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