Prediction of hotspots on 3D packages due to joule heating in Through Silicon Vias (TSV)

Market demand for smaller products with increased functionalities has been the driving force for 3D packages. Thermal management of 3D packages is challenging as the cooling solution need to access the intermediate dies within which is often difficult. In mobile application, the available space for cooling solution has also decreased dramatically. Numerical modeling of fine features such as vias also presents many difficulties as several decades of length scales occur simultaneously. In this paper, a methodology is used to overcome the difficulties by modeling the relevant length scales important to that level. As the model is reduced in length scale, boundary conditions from higher level are transferred to the lower level, ensuring energy balance between the levels. At the system level, external resistances can be estimated and a base temperature be used to determine system level thermal performance. At the package level, interconnect resistances and effects of depopulation are taken into account in determining maximum temperatures on die. At the die level, individual dies of the stack are modeled with distributed vias and actual temperature distribution is determined to investigate hotspots due to self heating. In a heatsink cooling solution, system level modeling showed that die temperatures are uniform at 49°C. Further modeling at package level showed that a 5.4°C temperature difference exists between the top and bottom memory dies due to interconnect thermal resistance. At the die level, the effect of Joule heating in copper vias on hotspot is studied. Joule heating is simulated with current densities of 125 to 175 A/cm². An increase in temperature can be seen but however, the effects of poor underfill thermal conductivity made the hotspot effects less pronounced.