A semi-formal methodology for the functional validation of an industrial DSP system

Author

Arditi, Laurent ; Clavé, Gaël

Author_Institution

Texas Instrum., Villeneuve Loubet, France

Volume

4

fYear

2000

fDate

2000

Firstpage

205

Abstract

This paper describes a new methodology allowing one to increase the efficiency of functional validation. The approach is based on a combination of simulation and formal techniques. It consists of first building formal models of digital hardware modules. The coverage of a test suite can then be accurately measured and new test cases are automatically generated to increase the coverage. This methodology has been applied during the development of a commercial DSP system. It has shown that, in spite of a very large test suite consisting of 300 million simulation cycles, there was still room for coverage improvement

Keywords

application specific integrated circuits; circuit CAD; digital signal processing chips; digital simulation; formal verification; hardware description languages; hardware-software codesign; integrated circuit design; digital hardware modules; formal models; formal techniques; functional validation; industrial DSP system; semi-formal methodology; simulation cycles; test cases; test suite; Automatic testing; Computer bugs; Design engineering; Digital signal processing; Formal languages; Formal verification; Hardware; Instruments; Postal services; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858724

Filename

858724