Warpage improvement for large die flip chip package

In the case of field programmable gate array (FPGA) chips, as the demand for higher speeds and enhanced functionality increases, the size of the flip chip die grows accordingly to offer higher number of logic cells. Large flip chip die also requires a large package for efficient signal routing. This paper shows a warpage improvement study including lid design and process optimization to solve warpage issue of large die FPGA flip chip packages with more fragile bump (23 * 23 mm die and 42.5 * 42.5 mm package). Though package warpage is well controlled for standard eutectic bump BOM (bill of materials) and process, it encountered problem when using higher Tg underfill, which is for better bump protection and reliability. A detailed finite element analysis was performed to simulate the effect of different lid structures (foot width, thickness etc) and lid materials (Cu, Al etc) on warpage. Actual units were built using improved lid structures and process. It was found that thicker Cu lid and lower underfill cure temperature are effective ways for warpage control, less than 8 mils warpage was achieved by lid design and process optimization for this 42.5 mm package with 23 mm die with more fragile bump.