Efficient module 2n+1 multiplication schemes for IDEA

In this paper we investigate different methods of designing a module 2ⁿ+1 multiplier in binary and diminished-1 systems for International Data Encryption Algorithm (IDEA^TM) block cipher and propose an efficient modulo 2ⁿ+1 multiplier. To design the different stages of the binary multiplier different methods are studied and compared. A new (5:3) counter for the reduction of Wallace tree delay is proposed and a modified diminished-1 algorithm is also proposed. The superiority of diminished-1 system rather than binary system for 2ⁿ+1 module multiplication is shown. We compare our results with previous works in terms of time and area