Performance evaluation of Galois Field arithmetic operators for optimizing Reed Solomon Codec

A series of experiments has been conducted to show that efficiency improvement in Galois Field (GF) operators does not directly correspond to the system performance at application level. The experiments were motivated by so many research works focusing on performance improvement of GF operators. Numerous variants of operators were formed based on various combination of operation types (multiplication, division, inverse, square), representation basis (Polynomial, Normal, Dual), and processing types (serial, parallel). Each of the variants has the most efficient form in either time (fastest) or space (smallest occupied area) when implemented in FPGA chips. In fact, GF operators are not utilized individually, rather integrated one to the others in implementing algorithms, mostly in error correction codes and cryptography applications. The experiments based on the implementation of Reed Solomon Encoder and Decoder RS(15,11) 4-bit using VHDL by means of two synthesis tools the Xilinx ISE 8.2i and the Altium ProChip Designer concludes that application performance mainly depends on the composition and distribution of the operators as well as their interaction and interconnection within the system architecture.