• DocumentCode
    3529238
  • Title

    Investigations in polysilicon CMP to apply in sub-quarter micron DRAM device

  • Author

    Koh, Jeong Deog ; Suh, Dae Won ; Han, Dong Won ; Kim, Jin Woong ; Park, Nae Hak ; Han, Sang Beom

  • Author_Institution
    R&D Div., Hyundai Microelectron. Co. Ltd., Cheongju, South Korea
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    214
  • Lastpage
    217
  • Abstract
    The chemical mechanical polishing (CMP) of polysilicon is an important technique to form polysilicon plugs or damascene lines in a sub-quarter micron DRAM device. The removal of polysilicon by CMP can reduced the recess in polysilicon plugs compared with conventional reactive ion etch (RIE). Furthermore, the damascene line scheme of polysilicon prevents serious voids formation and significant amounts of recess in inter layer dielectric (ILD) before formation of the contact. We discuss the characteristics of polysilicon CMP and the post cleaning process. In this paper, we also compared the performance of the polysilicon plug with that of the polysilicon damascene line by CMP
  • Keywords
    CMOS memory circuits; DRAM chips; VLSI; chemical mechanical polishing; elemental semiconductors; integrated circuit technology; silicon; 0.25 micron; ILD; Si; chemical mechanical polishing; damascene lines; inter layer dielectric; polysilicon CMP; polysilicon plugs; post cleaning process; sub-quarter micron DRAM device; Atomic layer deposition; Atomic measurements; Chemicals; Cleaning; Etching; Plugs; Random access memory; Rough surfaces; Surface contamination; Surface roughness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI and CAD, 1999. ICVC '99. 6th International Conference on
  • Conference_Location
    Seoul
  • Print_ISBN
    0-7803-5727-2
  • Type

    conf

  • DOI
    10.1109/ICVC.1999.820881
  • Filename
    820881