• DocumentCode
    3531417
  • Title

    3-D Parasitic Modeling for Rotary Interconnects

  • Author

    Honkote, Vinayak ; More, Ankit ; Taskin, Baris

  • Author_Institution
    Dept. of ECE, Drexel Univ., Philadelphia, PA, USA
  • fYear
    2012
  • fDate
    7-11 Jan. 2012
  • Firstpage
    137
  • Lastpage
    142
  • Abstract
    Resonant rotary clocking is a high-frequency, low-power technology for high performance integrated circuits (IC). The implementation of the rotary clocking technology requires long interconnects with varying geometric shape segments on the chip, which are modeled by transmission lines. The parasitics exhibited by the transmission line interconnects play a major role in characterizing the high frequency operation. To this end, the impact of parasitics on the operating characteristics of the rotary rings due to the different interconnect segments are identified. The interconnect parasitics are analyzed using a 3D finite element method based full wave electromagnetic analysis. Simulations performed for the rotary ring with 3D full wave based parasitic analysis results in 23.68% reduced clock frequency when compared with a conventional 2D based parasitic analysis. The power dissipated on the rotary ring simulated using the 3D full wave based parasitic analysis is around 84% less than the clock tree and is within 5% of the power dissipated on the ring simulated using the 2D based parasitic analysis.
  • Keywords
    clocks; finite element analysis; integrated circuit interconnections; integrated circuit modelling; three-dimensional integrated circuits; 3D finite element method; 3D full wave based parasitic analysis; 3D parasitic modeling; conventional 2D based parasitic analysis; electromagnetic analysis; geometric shape segments; high performance integrated circuits; resonant rotary clocking technology; rotary interconnects; transmission line interconnects; Clocks; Inductance; Integrated circuit interconnections; Integrated circuit modeling; Power transmission lines; SPICE; Topology; interconnects; resonant clocking; simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2012 25th International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4673-0438-2
  • Type

    conf

  • DOI
    10.1109/VLSID.2012.60
  • Filename
    6167742