Wirebond Vs. flip chip design of high speed 3D stacked memory packages

Author

Yazdani, Farhang

Author_Institution

BroadPak Corp., Santa Clara, CA, USA

fYear

2010

fDate

3-4 Aug. 2010

Firstpage

332

Lastpage

336

Abstract

3D Memory package-on-package stacking has gained popularity due to increase in demand for bandwidth, higher density and miniaturization. Challenges in design of high performance 3D stacks have increased with amplification in speed and signal integrity issues. This paper dissects the design elements of 3D memory stacks architecture and characterizes the signal integrity and trade off of wirebond and flip-chip stacks for high data rate applications. Signal integrity characterization of up to 10 stacked packages in both wirebond and flip chip configurations are presented. Effect of BGA stacking, transmission line and wirebond vs flip chip design in both time and frequency domains are analyzed and presented.

Keywords

electronics packaging; flip-chip devices; lead bonding; BGA stacking; flip chip design; high speed 3D stacked memory packages; package-on-package stacking; signal integrity characterization; transmission line; wirebond; Bandwidth; Chip scale packaging; Dielectric constant; Dielectric losses; Flip chip; Frequency domain analysis; Signal design; Stacking; Transmission lines; Wires; 3D packaging; BGA; CSP; DDR3; PBGA; PCIE; POP; SIP; SSO; Ser-Des; System in Package; Xaui; cavity down; die; electromagnetic; eye diagram; flip chip; high speed; interconnect; jitter; memory module; memory stacking; modeling; package on package; package stacking; resonance; signal integrity; silicon; substrate; thermal; wirebond;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on

Conference_Location

Penang

Print_ISBN

978-1-4244-7809-5

Type

conf

DOI

10.1109/ASQED.2010.5548315

Filename

5548315