Design and performance evaluation of Hybrid Prefix Adder and carry increment adder in 90nm regime

This paper presents an implementation of two 8-bit adders (HPA and CIA) and comparing their performance with respect to power delay product for different voltages in 90 nm regime. HPA is derived from Parallel prefix adders for minimized Power Delay product. CIA is derived from carry select adder with reduced area scheme for carry-select adders lowers this overhead by computing the carry and sum bits for a block-carry-in value of 0 only and by incrementing them afterwards depending on the final block-carryin. For 8-bit implementation of carry generation, HPA needs 158 transistors where as CIA needs 282 transistors. HPA gives reduced power delay product compared to CIA. Tanner EDA tool is used for schematic implementation and simulating the adder designs in the 90 nm technology.