A 1.6 GHz downconversion sampling mixer in CMOS

Author

Jakonis, Darius ; Svensson, Christer

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This paper describes a downconversion sampling mixer design in CMOS. A MOS switch linearization technique is utilized, which enables high frequency sampling of an RF signal. The measurement results show a 1.6 GHz input signal downconversion with a sampling rate of 1.55 GHz, +22 dBm IIP₃, 1.4 ps sampling jitter, 8 dB conversion loss and 25 dB noise figure. The chip is fabricated in a 0.35 μm 3.3 V CMOS process and bonded directly onto a printed circuit board. The downconversion sampling mixer occupies an active area of 0.05 mm² and consumes 43 mW power.

Keywords

CMOS integrated circuits; UHF mixers; integrated circuit bonding; integrated circuit design; integrated circuit measurement; jitter; linearisation techniques; signal sampling; 0.35 micron; 1.4 ps; 1.55 GHz; 1.6 GHz; 25 dB; 3.3 V; 43 mW; 8 dB; CMOS mixer; MOS switch linearization technique; PCB bonded chip; RF signal high frequency sampling; conversion loss; downconversion sampling mixer; noise figure; sampling jitter; sampling rate; Frequency; Jitter; Linearization techniques; Loss measurement; Noise figure; Noise measurement; Sampling methods; Semiconductor device measurement; Signal sampling; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205666

Filename

1205666