DocumentCode
3535583
Title
A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations
Author
Cassia, Marco ; Shah, Peter ; Bruun, Erik
Author_Institution
Tech. Univ. Denmark, Lyngby, Denmark
Volume
1
fYear
2003
fDate
25-28 May 2003
Abstract
A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
Keywords
cellular radio; circuit simulation; phase locked loops; sigma-delta modulation; GSM applications; linear model; overall phase noise; sample/hold block; simulation methodology; spur-free fractional-N ΣΔ PLL; Clocks; Delay; GSM; Phase locked loops; Sampling methods; Switches; Synthesizers; Tin; Transfer functions; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205751
Filename
1205751
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