Multi-terminal pulsed force & sense ESD verification of I/O libraries and ESD simulations

Author

Druen, Stephan ; Streibl, Martin ; Esmark, Kai ; Domanski, Krzysztof ; Niemesheim, Josef ; Gossner, Harald ; Schmitt-Landsiedel, Doris

Author_Institution

Inst. of Tech. Electron., Tech. Univ. of Munich, Munich, Germany

fYear

2004

fDate

19-23 Sept. 2004

Firstpage

1

Lastpage

9

Abstract

A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13 um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.

Keywords

CMOS integrated circuits; circuit simulation; electric current measurement; electrostatic discharge; voltage measurement; CMOS technology; ESD chip-level simulation tool; I-O library; current distribution; multiterminal pulsed force; sense ESD verification; voltage distribution; CMOS technology; Electrical resistance measurement; Electrostatic discharge; Libraries; Measurement techniques; Protection; Pulse measurements; Rails; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Conference_Location

Grapevine, TX

Print_ISBN

978-1-5853-7063-4

Electronic_ISBN

978-1-5853-7063-4

Type

conf

DOI

10.1109/EOSESD.2004.5272589

Filename

5272589