Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers

Author

Kim, Jongsun ; Xu, Zhiwei ; Chang, M. Frank

Author_Institution

Electr. Eng. Dept., California Univ., Los Angeles, CA, USA

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

This paper presents a new multiple access bus interface for re-configurable memory systems based on Code-Division-Multiple-Access (CDMA) techniques. It features multiple I/O access by using a multi-level signaling with source synchronous clocking. New CDMA I/O transceivers capable of re-configuring multiple accesses with high bus concurrency, low bus latency and low channel power consumption are proposed and evaluated. A maximum data rate of 2.0 Gbps/pin has been achieved using a 0.18-um CMOS process and a supply voltage of 1.8 V.

Keywords

CMOS memory circuits; code division multiple access; memory architecture; reconfigurable architectures; system buses; telecommunication signalling; transceivers; 0.18 micron; 1.8 V; 2.0 Gbit/s; CDMA I/O transceiver; CMOS process; concurrency; latency; multilevel signaling; multiple access bus interface; power consumption; reconfigurable memory system; source synchronous clocking; Bandwidth; Clocks; Concurrent computing; Costs; Delay; Energy consumption; Frequency; Multiaccess communication; Random access memory; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205878

Filename

1205878