Design of ultra high-speed CMOS CML buffers and latches

Author

Heydari, Payam ; Mohavavelu, Ravi

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

A comprehensive study of ultra high-speed current-mode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, a new 20GHz regenerative latch circuit will be introduced. Experimental results show a higher performance for the new latch architecture compared to a conventional CML latch circuit at ultra high-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

Keywords

CMOS logic circuits; buffer circuits; current-mode logic; flip-flops; integrated circuit design; low-power electronics; very high speed integrated circuits; 20 GHz; CML buffers; CML latches; CMOS; current mode logic; design procedure; latch architecture; low-voltage applications; regenerative latches; tapered buffers; ultra high-speed ICs; Analytical models; CMOS logic circuits; Clocks; Inverters; Latches; Multiplexing; Resistors; Tail; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205938

Filename

1205938