DocumentCode
3540156
Title
A robust hardwired interwoven fault-masking technique
Author
Mukati, M. Altaf ; Akhtar, Pervez
Author_Institution
Dept. of Comput. Sci. & Eng., Bahria Univ., Karachi, Pakistan
fYear
2009
fDate
4-6 Aug. 2009
Firstpage
584
Lastpage
586
Abstract
The process technology scales below 100 nanometers at present. Such miniaturizations of components has created reliability-threats to the designers, specially in the case of critical or semi-critical systems, whose failures can bring catastrophes in terms of human or great financial losses. Reliable working of such be ensured. In this paper, first the causes of such reliability-threats have been discussed and then a robust fault-masking technique has been presented to improve the reliability of a system. The technique presented restricts a system, even to generate momentary errors.
Keywords
fault tolerant computing; integrated circuit reliability; logic gates; robust hardwired interwoven fault-masking technique; Aging; Circuit faults; Computer science; Humans; Redundancy; Reliability engineering; Robustness; Single event upset; System testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Applications of Digital Information and Web Technologies, 2009. ICADIWT '09. Second International Conference on the
Conference_Location
London
Print_ISBN
978-1-4244-4456-4
Electronic_ISBN
978-1-4244-4457-1
Type
conf
DOI
10.1109/ICADIWT.2009.5273970
Filename
5273970
Link To Document