DocumentCode
3540165
Title
Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip
Author
Ma, Sheng ; Jerger, Natalie Enright ; Wang, Zhiying
fYear
2012
fDate
25-29 Feb. 2012
Firstpage
1
Lastpage
12
Abstract
Routing algorithms for networks-on-chip (NoCs) typically only have a small number of virtual channels (VCs) at their disposal. Limited VCs pose several challenges to the design of fully adaptive routing algorithms. First, fully adaptive routing algorithms based on previous deadlock-avoidance theories require a conservative VC re-allocation scheme: a VC can only be re-allocated when it is empty, which limits performance. We propose a novel VC re-allocation scheme, whole packet forwarding (WPF), which allows a non-empty VC to be re-allocated. WPF leverages the observation that the majority of packets in NoCs are short. We prove that WPF does not induce deadlock if the routing algorithm is deadlock-free using conservative VC re-allocation. WPF is an important extension of previous deadlock-avoidance theories. Second, to efficiently utilize WPF in VC-limited networks, we design a novel fully adaptive routing algorithm which maintains packet adaptivity without significant hardware cost. Compared with conservative VC re-allocation, WPF achieves an average 88.9% saturation throughput improvement in synthetic traffic patterns and an average 21.3% and maximal 37.8% speedup for PARSEC applications with heavy network loads. Our design also offers higher performance than several partially adaptive and deterministic routing algorithms.
Keywords
network routing; network-on-chip; PARSEC applications; VC re-allocation scheme; VC-limited networks; adaptive routing algorithms; deadlock-avoidance theories; deterministic routing algorithms; network loads; networks-on-chip; packet adaptivity; synthetic traffic patterns; virtual channels; whole packet forwarding; Adaptive systems; Algorithm design and analysis; Hardware; Resource management; Routing; System recovery; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
Conference_Location
New Orleans, LA
ISSN
1530-0897
Print_ISBN
978-1-4673-0827-4
Electronic_ISBN
1530-0897
Type
conf
DOI
10.1109/HPCA.2012.6169049
Filename
6169049
Link To Document