Low complexity parallel Chien search architecture for RS decoder

Author

Hu, Qingsheng ; Wang, Zhigong ; Zhang, Jun ; Xiao, Jie

Author_Institution

Southeast Univ., Nanjing, China

fYear

2005

fDate

23-26 May 2005

Firstpage

340

Abstract

This paper presents a group-based optimization scheme for a parallel Chien search circuit in a RS (Reed-Solomon) (255,239) decoder. A novel global optimization algorithm (GOA) is presented to find out the common modulo 2 additions within groups of a Galois field (GF) multiplier. By pre-computing the common items, group-based GOA can reduce the area of parallel Chien search circuit by 44% compared to 23% if applying GOA to GF multipliers separately. The group-based optimization scheme can be widely used in a general parallel architecture in which a lot of GF multipliers are involved.

Keywords

Galois fields; Reed-Solomon codes; channel coding; decoding; optimisation; parallel architectures; search problems; (255,239) decoder; GF multipliers; Galois field; RS decoder; Reed-Solomon decoder; global optimization algorithm; group-based optimization; low complexity search architecture; modulo 2 additions; parallel Chien search circuit; parallel architecture; Circuits; Clocks; Decoding; Equations; Forward error correction; Galois fields; Parallel architectures; Polynomials; Reed-Solomon codes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464594

Filename

1464594