Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation

In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by an adaptive algorithm based on evolutionary computation. The hardware-based EDF version 1 consists of two submodules, that is, a filtering and fitness calculation (FFC) module and a reproduction and selection (RS) module. The FFC module has high computational ability to calculate the output and the fitness value since its submodules run in parallel. However, the hardware size of the FFC module is large, and many machine cycles are needed. Thus, in the hardware-based EDF version 2, we combine the two modules to reduce its hardware size and machine cycles. A synthesis result on the FPGA shows the clock frequency is 65.5 MHz and the maximum sampling rate of the hardware-based EDF version 2 is 4,948.1 Hz. Moreover, the hardware-based EDF version 2 is 15.7 times faster than the hardware-based EDF version 1.