DocumentCode
3541588
Title
Debugging of behavioral VHDL specifications by source level emulation
Author
Koch, Gernot ; Kebschull, Udo ; Rosenstiel, Wolfgang
Author_Institution
Forschungszentrum Inf., Karlsruhe Univ., Germany
fYear
1995
fDate
18-22 Sep 1995
Firstpage
256
Lastpage
261
Abstract
We present an approach to accelerate the validation speed of behavioral VHDL system specifications through the use of hardware emulation. The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by reading the registers of the circuit when a breakpoint is reached
Keywords
computer aided software engineering; computer debugging; development systems; formal specification; formal verification; hardware description languages; logic CAD; logic design; behavioral VHDL specification debugging; breakpoints; hardware emulation; source level debugging; source level emulation; validation speed; Acceleration; Application software; Circuits; Computer languages; Emulation; Formal verification; Hardware; Software algorithms; Software debugging; Superluminescent diodes;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location
Brighton
Print_ISBN
0-8186-7156-4
Type
conf
DOI
10.1109/EURDAC.1995.527415
Filename
527415
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